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NXP Semiconductors /LPC11Exx /SYSCON /SSP0CLKDIV

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Interpret as SSP0CLKDIV

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https://regviz.com/r/NXP Semiconductors/LPC11Uxx/SYSCON/SSP0CLKDIV#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIV0RESERVED

Description

SSP0 clock divider

Fields

DIV

SPI0_PCLK clock divider values. 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data